1. Field of the Invention
The invention relates to an operational amplifier for executing adding and subtracting operations, etc. of analog signals, particularly to an operational amplifier capable of supplying a large power approximate to a power supply voltage to a load resistance and of reducing the current consumption when a signal is not issued.
2. Description of the Related Art
There is a technique in this field, for example, as disclosed in Japanese Patent Laid-Open Publication No. 8-274551. An operational amplifier disclosed in this publication includes a differential amplifying stage, a first level shifting stage, a first amplifying stage, a second amplifying stage, a second level shifting stage and an outputting stage. An input signal is differentially amplified by the differential amplifying stage. The first level shifting stage level shifts an output of the differential amplifying stage in the direction of a second power supply voltage. The first amplifying stage amplifies an output of the first level shifting stage in opposite phase. The second amplifying stage amplifies the output of the differential amplifying stage in opposite phase. The second level shifting stage level shifts an output of the second amplifying stage in the direction of a first power supply voltage. The outputting stage comprises a p-channel MOS transistor (hereinafter referred to as PMOS) and an n-channel MOS transistor (hereinafter referred to as NMOS) for executing complementary operation in response to output signals of the first amplifying stage and the second level shifting stage. The PMOS constituting the outputting stage is driven by an output of the first amplifying stage. The NMOS constituting the outputting stage is driven by an output of the second level shifting stage.
However, there are following problems in the conventional operational amplifier. That is, a driving signal of the PMOS constituting the outputting stage is amplified through the first level shifting stage for level shifting the output of the differential amplifying stage in the direction of the second power supply voltage, the first amplifying stage for amplifying the output of the first level shifting stage in opposite phase, and the second level shifting stage for level shifting the output of the first amplifying stage in the direction of the second power supply voltage. Accordingly, it is difficult to set the dc voltage of the driving signal.
Since the dc voltage of the driving signal determines a current which flows through the outputting stage when a signal is not issued, namely, at the signal non-issuance time, it is necessary that this current is not varied largely owing to the variations of transistor characteristics during fabricating process and the change is power supply voltage. Accordingly, higher gain is not taken place from the differential amplifying stage to the second level shifting stage. As a result, it was necessary to render the ratio (W/L) of the channel width (W) of a transistor of the outputting stage with respect to the channel length (L) thereof large so as to render the channel conductance large in order to permit a large current to flow through the outputting stage. Further, on the grounds set forth above, the change in the power supply current relative to the change in the power supply voltage was large at the signal non-issuance time.
Accordingly, there has been desired so far an operational amplifier capable of supplying a large power approximate to a power supply voltage to a load resistance and of rendering the change in the consumption current relative to the power supply voltage low at the signal non-issuance time.